Symmetrical polyphase networks utilizing constant reactances

ABSTRACT

Symmetrical polyphase networks are disclosed comprising N single-phase networks each including a constant reactance, i.e, a reactance whose value remains constant with changes in the frequency of the signal applied thereto. Due to the use of this constant reactance (controlled constant current source, such as properly connected and controlled transistors, or impedance transformers), the polyphase network responds differently to input signals of negative and positive frequencies (a positive frequency is a counterclockwise sequence of vectors representing polyphase input signals and a negative frequency is a clockwise sequence of vectors representing polyphase input signals). Also the polyphase network has a different insertion loss characteristic depending on the sequence of the polyphase input signals.

Unite States Patent 72] Inventor Micahel John Gingell 2,984,799 /i96i Gerks 328/155 x ggz i zg England Primary ExaminerEli Lieberman [21] P 1969 Assistant Examiner-Paul L. Gensler [22] Flled a i Attorneys-C. Cornell Remsen,Jr.,WalterJ. Baum,PaulW. patmed I Sta d d El t C t Hemminger, Percy P. Lantzy, Philip M. Bolton, Charles L. [73] Asslgnee s s $222; Y n M ec orpm'a on Johnson, Jr. and Isidore Togut [32] Priority June 7, 1968 [33] Great Britain [31] 27,161/68 54 SYMMETRICAL POLYPHASE NETWORKS W; symlmethrical T "f l i g discmsed UTILIZING CONSTANT REACTANCES comprising sing e-p ase neltwor sleac inc u mg a constan}: 19 Claims 44 Drawing Figs reactance, re, a reactance w ose va ue rernams constant wit changes in the frequency of the signal applied thereto. Due to [52] [LS- C] 333/24, th use f thi t t reactance t ll d t t current 307/295, 333/ R, 333/ R. 332/4 source, such as properly connected and controlled transistors, [51] Int. Cl 03h 7/44 impedance transformers) the po|yphase network responds [50] Field of Search 333/1, 80, diff tl to input Signals Qfnegative and positive frequencies 30 1124, 324/107, 108; (a positive frequency is a counterclockwise sequence of vec- 336/5, 10, 12; 330/107 109 tors representing polyphase input signals and a negative frequency is a clockwise sequence of vectors representing [56] References cued polyphase input signals). Also the polyphase network has a UNITE TAT PATENTS different insertion loss characteristic depending on the 2,418,643 4/1947 Huge 336/5 sequence ofthe polyphase input signals.

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lnvenlor SYMMETRICAL POLYPI-IASE NETWORKS UTILIZING CONSTANT REACTANCES BACKGROUND OF THE INVENTION The invention relates to polyphase networks and more particularly to symmetrical polyphase networks.

SUMMARY OF THE INVENTION The term constant reactance" defined as a reactance whose value remains constant with changes in the frequency of the signal applied thereto.

The term positive frequency as employed herein is defined as a counterclockwise sequence of vectors representing polyphase input signals.

The term negative frequency as employed herein is defined as a clockwise sequence of vectors representing polyphase input signals.

An object of the present invention is to provide a symmetrical polyphase network including constant reactances.

Another object of the present invention is to provide a symmetrical polyphase network including constant reactances such that the symmetrical polyphase network responds differently to input signals of negative and positive frequencies.

A feature of the present invention is the provision of a symmetrical polyphase network comprising N single-phase networks, one for each phase of an N-phase input signal, where N is an integer greater than one; each of said single-phase networks including at least one constant reactance so that the symmetrical polyphase network responds differently to input signals of negative and positive frequencies.

BRIEF DESCRIPTION OF THE DRAWING The above-mentioned and other features and objects of this invention will become more apparent by reference to the following description taken in conjunction with the accompanying drawings, in which:

FIGS. MA) and 1(B), respectively, illustrate positive and negative sequence four-phase vector diagrams;

FIG. 2 illustrates a positive sequence four-phase vector diagram;

FIG. 3( A) illustrates the frequency response curve of a sim ple thirdorder elliptic low-pass filter;

FIG. 3( B) illustrates the frequency response curve illustrated in the drawing according to FIG. 3( A) transformed into an asymmetric form;

FIG. 4 shows the gyrator realization FIG. 5 shows the controlled source tor;

FIG. 6 shows a method of realizing constant reactances in a founphase system;

FIG. 7 shows the circuit diagram of a single-phase asymmetric-about-zero frequency filter;

FIG. 8 shows the circuit diagram of the polyphase realization of the circuit diagram of FIG. 7 for a two-phase system with quadrature inputs;

FIGS. 9( A) and 9( B), respectively, show circuit diagrams of the theoretical and practical realizations of a two-phase 1 to j impedance transformer of the voltage shift type;

FIGS. I0(A) and 10(B), respectively, show circuit diagrams of the theoretical and practical realizations of another twophase voltage shift type I to j impedance transformer;

FIGS. II(A) and 11(8), respectively, show circuit diagrams of the theoretical and practical realizations of a two-phase I to j impedance transformer of the current shift type;

FIGS. 12(A) and I2(B),-r espectively, show circuit diagrams of the theoretical and practical realizations of another twophase current shift type 1 to j impedance transformer;

FIG. I3 shows the circuit diagram of a single-phase network which utilizes a plurality of constant reactances;

FIG. 14 shows the circuit diagram of the polyphase realization of the circuit diagram to FIG. 13 for a two-phase network with quadrature inputs;

FIG. 15 shows part of the circuit diagram of FIG. I4 together with negative impedance converters;

as employed herein is of constant reactance; representation of a gyra FIGS. 16, I7, 18 and 20, respectively, show the practical circuit diagrams of different forms of three-phase impedance transformers;

FIG. I9 shows the equivalent circuit diagram of one phase of the impedance transformer shown in FIG. 18;

FIG. 21 shows the circuit diagram of another single-phase network which utilizes a plurality of'constant reactances;

FIG. 22 shows the circuit diagram of the polyphase realization of the circuit diagram of FIG. 2R for a three-phase network;

FIGS. 23 and 24 show equivalent circuit diagrams of one phase of the circuit diagram shown in FIG. 22;

FIGS. 25 and 26 show the circuit diagrams of difierent forms of four-phase impedance transfonners;

FIGS. 27(A) and 27(B) show frequency response curves;

FIGS. 28(A) and 28(8) show circuit diagrams of a singlephase filter before and after transformation by image design techniques;

FIGS. 29(A) and (B) show frequency response curves for an N-path frequency translation system having low-pass filters connected in each of the N-paths thereof;

FIGS. 30(A) and (B) show frequency response curves for an N-path frequency translation system which utilizes the symmetrical polyphase networks according to the invention;

FIGS. 31(A) to (C) show vector diagrams; and quadrature inputs.

FIG. 32 shows the circuit diagram of a two-phase network with quadrature inputs.

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to understand the operation of the symmetrical polyphase networks according to the present invention. the concept of negative frequency must be introduced. If a fourphase system is considered, which has as shown in FIG. I(A) voltages of V, '"jV, V, +jV applied to its four input terminals, then the input signal can be called symmetrical, since all voltages are equal in magnitude and spaced apart by steps of and of say positive sequence, since, conventionally, all vectors rotate anticlockwise and the voltage on path 1 leads the voltage on path 2 by 90, and similarly, the voltage on path 2 leads the voltage on path 3 by 90, etc. If now the vectors rotate the opposite way, i.e., as shown in FIG. 1(8), the system is still symmetrical, but is now of negative sequence (negative frequency), since the voltage on path I lags the voltage on path 2 by 90 instead of leading as before.

Considering the voltage on path I it can be seen from FIG. 2 that this voltage is V sin wt, i.e., the projection of the vector 1 onto the imaginary axis when it is being rotated counterclockwise. When the sequence of vectors is reversed, -V sin cut will be observed. Since -sin wl==sin (wr), it can be said that, in a single-phase network, a positive sequence represents a positive to and a negative sequence represents a negative (0. Thus, where positive and negative frequencies are hereinafter referred to with reference to the characteristics of a singlephase network, it means positive and negative sequence, respectively, in a polyphase network containing N singlephase networks.

In order to realize a polyphase network which has different magnitude responses to positive and negative sequence (positive and negative frequency) inputs, it is easiest to first consider a single-phase network having different magnitude responses to positive and negative frequencies. By its very nature such a single-phase network will not be physically realizable, since it is not possible to distinguish between positive and negative frequencies in a single-phase network containing real components. However, consideration of an asymmetricabout-zero frequency single-phase network can be used as a stepping stone to the synthesis of a polyphase network where positive and negative frequencies have a real significance and it will be seen that interconnections between the single-phase networks, so that each network knows" what sequence of input has been applied, is necessary and sufiicient for polyphase realization of the previously unrealizable single phase network.

where w is the frequency scale of the original filter, and

Q is a new frequency scale,

the response is transformed into the asymmetric form illustrated in FIG. 3(B). As shown in FIG. 3(B) w, w so that the peak that was at (0,, (see FIG. 3(A)) is shifted to Q= (see FIG. 3(B)). It is now possible to observe the effect of the above on realizability. The inverse transform of equation (I) is given by Since the original network would have been constructed of coils and capacitors and resistively terminated, a coil which had an admittance of l/jwL would, therefore, be transformed as below:

1 1Q/w 1 1 M 1 1 ML (3) The coil has, therefore, been transformed into a coil in parallel with a constant reactance. Similarly, a capacitor C would be transformed into a capacitor C in series with a constant reactance. However, since constant reactances are physically unrealizable in single-phase networks, the single-phase network is also unrealizable. "i'n th t yphase network according to the present invention, which contains N single-phase networks, it is possible to realize the constant reactance elements by means of, for example, gyrators, or sets of controlled sources, the latter being N-port gyrators.

Consider a two-phase system with quadrature inputs of V and V,,,. At any point in one of the two paths of the system there will be a voltage of V and a current of I. Since the two paths are physically identical, there will be at the corresponding point in the other of the two paths a voltage of V and a current ofjI.

Thus, if gyrator G1 is connected between the two phases, the two single-phase networks, in a symmetrical way as shown in FIG. 4, for example, it will have a voltage of V across port and a voltage of 'V across port 6. The gyrator must be symmetrical. V

A symmetrical gyrator has the chain matrix Vl L! V2 gm I; gm 0 I2 i.e., 1 =gmV- and I l-gmI 1 Therefore, it can be seen from equations (6) and (7) that looking into either port of gyrator G1 a reactance of l/jgm is observed. Also, since the gyrator is a lossless element (theoretically), it is possible to construct lossless networks with their attendant low sensitivity (compared with active and passive R-C networks).

As shown in FIG. 5, gyrator G2 can be represented by two controlled sources, i.e., the constant current sources CCSl and CCS2.

By using this representation, it is possible to envisage ways of extending the use of gyrators in systems having more than two phases. FIG. 6 shows a way of realizing constant reactances in a four-phase system with what is virtually a fourport gyrator.

For other than two or four phases, the arrangements are slightly more involved due to the complex relationship between voltages and currents of the single-phase circuits.

In practice the gyrator circuits are realized with transistors. As an example of the application of the above principles, consider the filter described hereinabove with reference to FIG. 3(8).

The single-phase version of this filter could take the form shown in FIG. 7 wherein coil Ll which is connected between one input and one output terminal is shunted by constant reactance X3 and capacitor C2, constant reactance X2 and capacitor C3 connected in series. The input terminals of the filter are shunted by capacitor C1 connected in series with constant reactance X1 and the output terminals are shunted by capacitor C4 connected in series with constant reactance X4.

The polyphase realization for a two-phase system with quadrature inputs is shown in FIG. 8 where it can be seen that four two-port gyrators G3 to G6 are utilized for the constant reactances of each one of the two phases.

One port of two-port gyrator G3 is used for one phase and is, therefore, connected in series between capacitors C2 and C3 across coil Ll, while the other port of this gyrator is used for the other phase and is, therefore, connected in series between capacitors C2 and C3 across coil L1 Similarly, the two-port gyrators G4 to G6 each have each one of the two ports thereof utilized for one of the two input phases, i.e., two ports of gyrator G4 are utilized with capacitors Cl and C1 to shunt the inputs of the two phases, the two ports of gyrator G5 are used to shunt coils Ll and L1 and the two ports of gyrator G6 is utilized with capacitors C4 and C4 to shunt the outputs of the two phases.

The gyrators and N-port gyrators used to realize constant reactances may be called polyphase-constrained networks, since the N terminals thereof are forced to carry voltages and currents which are always in N phases.

A further class of polyphase-constrained networks are those which include I to j impedance transformers to provide the constant reactances, where j is he conventionally employed mathematical symbol equal toV 1(See page 479, The International Dictionary of Physics and Electronics," 1956).

By way of example, consider the circuit diagram shown in FIG. 9(A) which shows a two-phase (quadrature) I to j impedance transformer of the voltage shift type having a constant current source (CCS3 or CCS4) in each phase thereof and the voltages and currents associated with each phase are as indicated. The phrase I to j impedance transformer" means if impedances Z are placed on the output of each phase, in other words, looking into the inputs of the impedance transformer, impedances of 12 will be seen looking into either input from the output of the impedance transformer.

These networks which may be utilized as circuit elements to transform resistors into constant reactances are in practice realized with transistors as shown in FIG. 9(8). Each one of the two phases contains a transistor, i.e., transistors VTl and VT2, having their collector-emitter circuits connected in series between the input and output terminals of the network.

The V, voltage input to one of the two phases is also applied to the base of transistor VTl in the other of the two phases by means of transistor VT3 having its base connected to the jV, voltage source, its collector connected to the base of transistor VTI and to a negative electrical power supply via resistor R1 and its emitter connected to ground potential via resistor R2. The input voltage V, is applied directly to the base of transistor VTZ.

Alternatively, the two-phase voltage shift type I to j impedance transformers may take the form shown in FIGS. (A) and 10(3). The equivalent circuit diagram of FIG.

- 10(A) shows the voltages and currents associated with each phase and the practical circuit diagram of FIG. 10(8) comprises a transistor in each one of the two phases, i.e., transistors VT4 and VT5 having their emitter-collector circuits connected in series between the input and output terminals of the network.

The V, voltage output of one of the two phases is applied directly to the base of transistor VT4 and the output voltage V, of the other of the two phases is applied to the base of transistor VT5 in said one of the two phases by means of transistor VT6 having its base connected to the collector of transistor VT4, its collector connected to a negative electrical power supply via resistor R11 and to the base of transistor VT5 and its emitter connected to ground potential via resistor R10.

Examples of two-phase (quadrature) current shift types of 1 to j impedance transformers are shown in FIGS. 11(A) and 11(8) and FIGS. 12(A) and 12(B).

FIGS. 11(A) and 12(A) show the theoretical circuit diagrams and indicate the voltages and currents associated with each phase and do not require any further explanation.

FIG. 11(8) shows the practical circuit diagram for the theoretical circuit of FIG. ll(A) and comprises a transistor in each one of the two phases, i.e., transistors VT7 and VT8 having their emitter-base circuits connected in series between the input and output terminals of the network.

The base of the transistor VT7 is directly connected to the collector of transistor VT8 and the base of transistor VT8 is connected to the collector of transistor VT7 via transistor VT9 having its emitter connected to earth potential via resistor R12, its collector connected to the base of transistor VT8 and its base connected to the collector of transistor VT7 and to a positive electrical power supply via resistor R13.

FIG. l2(B) shows the practical circuit diagram for the theoretical circuit of FIG. 12(A) and comprises a transistor in each one of the two phases, i.e., transistors VT10 and VTll having their base-emitter circuits connected in series between the input and output terminals of the network.

The base of transistor VTIO is connected to the collector of transistor VTll via transistor VT12 having its emitter connected to ground potential via resistor R15, its base connected to a positive electrical power supply via resistor R14 and to the collector of transistor VT] 1, and its collector directly con nected to the base of transistor VTltl. The base of the transistor VTlll is directly connected to the collector of transistor VTlll.

FIG. 13 shows the circuit diagram of a single-phase network which utilizes a large number of constant reactances X5, X6, X7, X8, X9...XM. The input to the network is shunted by capacitor C5, the output of the network is shunted by capacitor CN and constant reactances X6, X8...X(M-l) are respectively connected in series with capacitors C6, C7...C(N-l) between ground potential and the junction of the constant reactances X5 and X7, X7 and X9...X(M2) and XM.

By utilizing any one of the l toj impedance transformers outlined in the preceding paragraphs, the polyphase version of the circuit diagram of FIG. 13 is shown in FIG. 14. This is a two-phase (quadrature) network having input phases ,and I and input voltages V,, and jV,,,.

The input to the single-phase circuits for D, and I are, respectively, shunted by capacitors C5, and C5 while their outputs are respectively shunted by capacitors CN, and CN Since the l to j impedance transformers can be utilized as circuit elements to transform resistances into constant reactances, the T-networks of resistors R5,, R7,, and R6,, and resistors R5 R7 and R6 are utilized in conjunction with the j to l impedance transformer 2 which is interposed between resistors R6,, R6 and capacitors C6,, C6, to provide the constant reactances X5, X6 and X7 of FIG. 13 in each phase of the two-phase network of FIG. 14.

Similarly, the j to l impedance transformer 3 is utilized in conjunction with the T-networks of resistors R(M-2),, RM, and R(Ml), and resistors R(M2),, RM and R(Mll), to provide the constant reactances X(M2), XM and X(Mll) of FIG. 13 in each phase of the two-phase network of FIG. 14.

The l to j impedance transformer ll interposed between the inputs to the network and resistors R5, and R5 is utilized to phase shift the inputs by j before they pass through the network and the l to j impedance transformer 4 interposed between resistors RM, and RM, and the outputs from the network corrects this phase shift before the signals are passed to the outputs of the network.

If, as is common, the reactances X6, X8, etc. are of opposite sign to the reactances X5, X7, X9, etc, it would be necessary to add negative impedance converters to the circuit diagram of FIG. 14 as shown in the circuit diagram of FIG. 15. Referring to FIG. 15, part of the circuit diagram of FIG. M is shown therein and includes negative impedance converters 5 and 6 which are, respectively, interposed between resistors R6, and the junction of resistors R5, and R7, and resistor R6, and the junction of resistors R5 and R7 Due to the use of the negative impedance converters which would be included in each of the resistance T-networks, it is necessary to change the j to 1 impedance transformers to I to j impedance transformers, e.g., transformer 7 (FIG. 15) for transformer 2 (FIG. 14).

The circuit diagram shown in FIG. 14 without the capacitors can be considered as an N'port gyrator which is lossless and passive although it may have to contain active devices to enable it to be realized.

FIGS. I6, 17, I8 and 20 show examples of practical circuit arrangements for three-phase constrained networks.

The three-phase constrained network according to FIG. 16 comprises a transistor in each of the three phases, each of the single-phase networks, i.e., transistors VTI3 to VTlS having their collector-emitter circuits connected in series between the input and output terminals of the network. The base of transistor VT13 is connected to the collector of transistor VTIIS, the base of transistor VTI4 is connected to the collector of transistor VTI3 and the base of transistor VTlS is connected to the collector of transistor VT14.

This network which can be considered as a I to h impedance transformer has the chain matrix where Z, input impedance Z output impedance The three-phase constrained network of FIG. 17 is basically the same as the network of HG. 16 except the bases of each of the transistors VT13 to VT are connected to the collector of the transistor in the subsequent instead of the preceding ad jacent phase to provide a I to l/h impedance transformer i.e., the base of transistor VT14 is connected to the collector of transistor VT15, the base of transistor VT15 is connected to the collector of transistor VT13 and the base of transistor VT13 is connected to the collector of transistor VT14.

This network has the chain matrix FIG. 18 shows the practical circuit diagram of the threephase constrained network which includes a transistor in each of the three phases, i.e., transistors VT16 to VT18 having their collector-emitter circuits connected in series between the input and output terminals of the network.

The interconnections between the three phases in order to provide a I toj'\/5 impedance transformer is effected by three networks which each include a transistor, i.e., the transistors VT19 to VT21 having their collectors connected to a negative electrical supply and their emitters connected to ground potential, respectively, via bias resistors R17, R18 and R19.

The base of transistor VT19 is connected to the input voltage V of one of the phases, i.e., to the collector of transistor VT16, the base of transistor VT20 is connected to the input voltage hV of another one of the phases, i.e., to the collector of transistor VT17 and the base of transistor or VT21 is connected to the input voltage h V of the other of the phases, i.e., to the collector of transistor VT18.

The emitter of transistor VT19 is also connected to the emitter of transistor VT20 via resistor R16 connected in series with resistor R16/2 and to the emitter of transistor VT21 via resistor R21/2 connected in series with a resistor R21. The junction of resistors R21 and R21/2 is connected to the base of transistor VT18 and the junction of resistors R16/2 and R16 is connected to the base of transistor VT16.

The emitter of transistor VT20 is also connected to the emitter of transistor VT21 via resistor R20 connected in series with resistor R20/2 and the junction of resistors R20 and R20/2 is connected to the base of transistor VT17.

The value of the resistances R16, R20 and R21 are arranged in conjunction with the transistors VT19 to VT21 such that a voltage of jV 3 is applied to the base of transistor VT16, a voltage of hjV, is applied to the base of transistor VT17 and a voltage hjV is applied to the base of transistor VT18.

This network has the chain matrix and I i-Rl (17) and From equations (17), (18) and (19) (V hV i R16 Vl From equations (10) and (20) The three-phase constrained network of FIG. 20 is basically the same as the network of FIG. 18 except the three networks which each include one of the transistors VT19 to VT21 are .arranged such that a l to j 3 impedance transformer is pro- :vided, i.e., resistors R16/2, R20/2 and R21/2 are, respectively, replaced by resistors 2Rl6, 2R20 and 2R21, the junction of resistors R16 and 2Rl6 is connected to the base of transistor VT17, the junction of resistors R20 and 2R20 is connected to the base of transistor VT18 and the junction of resistors R21 and 2R21 is connected to the base of transistor VT16.

This network has the chain matrix The electrical supply arrangements for each of the phases (single-phase networks) of the circuit diagrams of FIGS. 16, 17, 18' and 20'are not shown, but in practice would be arranged such that a predetermined potential difference exists between the collector and emitter, and the emitter and base of each of the transistors which form part of each of the phases. An example of how this may be achieved in practice will be outlined in a subsequent paragraph.

FIG. 21 shows the circuit diagram of a single-phase network which utilizes constant reactances X10 to X12. The input to the network is shunted by capacitor C8, the output is shunted by capacitor C9 and the constant reactance X12 is connected in series with capacitor C10 between ground potential and the junction of reactances X10 and X11. It is assumed that the constant reactance X12 is of opposite sign to the constant reactances X10 and X11.

By utilizing the l to h impedance transformers shown in FIG. 16, the three-phase version of the circuit of F 1G. 21 is shown in F 1G. 22.

Referring to FIG. 22, constant reactance X10 is provided in each phase by the l to It impedance transformer enclosed by the chain dotted line 11A and resistors R10 and R10 for 

1. A symmetrical polyphase network comprising: N single-phase networks, a different one coupled to each phase of an N-phase input signal, where N is an integer greater than one; each of said single-phase networks including at least one constant reactance so that said polyphase network responds differently to input signals of negative and positive frequencies, the reactance value of said constant reactance being different than zero.
 2. A polyphase network according to claim 1, wherein each of said constant reactances includes an N-port symmetrical gyrator, each of said N ports being coupled to a different one of said single-phase networks.
 3. A polyphase network according to claim 1, wherein each of said constant reactances includes an N-phase l to j impedance transformer, where j is equal to -
 4. A polyphase network according to claim 3, wherein said impedance transformer includes N circuits each having a transistor with its collector-emitter circuit connected in series between the input and output terminals of its associated one of said circuits, and its base coupled to the collector of said transistor in another one of said circuits.
 5. A polyphase network according to claim 4, wherein N is equal to four; and the base of said transistor in one of said circuits is directly connected to the collector of said transistor in another of said circuits receiving as an input signal a signal lagging in phase with respect to the phase of the input signal coupled to said one of said circuits.
 6. A polyphase network according to claim 4, wherein N is equal to two; said transistor of one of said circuits includes a first transistor; and said transistor of the other of said circuits includes a second transistor, the base of said second transistor being directly connected to the collector of said first transistor; and further including a third transistor network coupling the base of said first transistor to the collector of said second transistor.
 7. A polyphase network according to claim 6, wherein said third transistor network includes a third transistor, an electrical power supply, a first resistor coupling the emitter of said third transistor to one terminal of said power supply providing a given potential, means directly connecting the collector of said third transistor to the base of said first transistor, a second resistor coupling the collector of said third transistor to the other terminal of said power supply providing a potential lower than said given potential, and means directly connecting the base of said third transistor to the collect or of said second transistor. 8 A polyphase network according to claim 4, wherein N is equal to three; and further including a fourth transistor network couPling the collector of said transistor of each of said circuits to the base of said transistor of an adjacent one of said circuits.
 9. A polyphase network according to claim 8, wherein said fourth transistor network coupled to two adjacent ones of said circuits includes an electrical power supply, a fourth transistor having its base directly connected to the collector of said transistor in one of said two adjacent ones of said circuits and its collector directly connected to one terminal of said power supply providing a given potential, a first resistor coupled between the emitter of said fourth transistor and the other terminal of said power supply providing a potential greater than said given potential, and a potentiometer coupled between the emitter of said fourth transistor and the base of said transistor in the other of said two adjacent ones of said circuits, said potentiometer including a second resistor having a first terminal connected to the emitter of said fourth transistor and a second terminal, and a third resistor having a first terminal directly connected to said second terminal of said second resistor and a second terminal connected to the emitter of a transistor included in said fourth transistor network coupled to another two adjacent ones of said circuits, said second resistor having a value one-half of the value of said third resistor, the base of said transistor in said other of said two adjacent ones of said circuits being directly connected to said second terminal of said second resistor and said first terminal of said third resistor.
 10. A polyphase network according to claim 3, wherein N is equal to two; and said impedance transformer includes two circuits each having a transistor with its emitter-base circuit connected in series between the input and output terminals of its associated one of said circuits; the base of said transistor in one of said circuits being directly connected to the collector of said transistor in the other of said circuits; and a third transistor network coupling the base of said transistor in said other of said circuits to the collector of said transistor in said one of said circuits.
 11. A polyphase network according to claim 10, wherein said third transistor network includes a third transistor, an electrical power supply, a first resistor coupling the emitter of said third transistor to one terminal of said power supply providing a given potential, means directly connecting the base of said third transistor to the collector of said transistor of said one of said circuits, a second resistor coupling the base of said third transistor to the other terminal of said power supply providing a potential higher than said given potential, and means directly connecting the collector of said third transistor to the base of said transistor in said other of said circuits.
 12. A polyphase according to claim 1, wherein each of said constant reactances includes an N phase 1 to -j impedance transformer, where j is equal to -1.
 13. A polyphase network according to claim 12, wherein N is equal to four; and said impedance transformer includes four circuits each having a transistor with its collector-emitter circuit coupled in series between the input and output terminals of its associated one of said circuits and its base connected to the collector of said transistor in an adjacent one of said circuits receiving as an input signal a signal leading in phase with respect to the phase of the input signal coupled to said associated one of said circuits.
 14. A polyphase network according to claim 12, wherein N is equal to three; and said impedance transformer includes three circuits each having a transistor with its collector-emitter circuit coupled in series between the input and output terminals of its associated one of said Circuits, and a fourth transistor network coupling the base of said transistor of said associated one of said circuits to the collector of said transistor of said associated one of said circuits.
 15. A polyphase network according to claim 14, wherein said fourth transistor network includes an electrical power supply, a fourth transistor, means directly connecting the base of said fourth transistor to the collector of said transistor of said associated one of said circuits, means directly connected to one terminal of said power supply providing a given potential, a first resistor coupling the emitter of said fourth transistor to the other terminal of said power supply providing a potential higher than said given potential, a second resistor coupling the emitter of said fourth transistor to the base of said transistor of said associated one of said circuits, and a third resistor coupling the junction of said second resistor and the base of said transistor of said associated one of said circuits to the emitter of a transistor included in said fourth transistor network of an adjacent one of said circuits, the value of said third resistor being one-half the value of said second resistor.
 16. A polyphase network according to claim 1, wherein N is equal to three; and said constant reactance includes a three-phase impedance transformer of one of a three-phase l to h impedance transformer and a three-phase l to 1/h impedance transformer, where h is equal to e j2
 3. 17. A polyphase network according to claim 16, wherein both of said l to h and l to 1/h impedance transformers include three circuits each having a transistor with its collector-emitter circuit coupled in series between the input and output terminals of its associated one of said circuits and its base directly connected to the collector of said transistor of an adjacent one of said circuits; a source of voltage V coupled to the first of said circuits; a source of voltage Vh coupled to the second of said circuits; and a source of voltage Vh2 coupled to the third of said circuits.
 18. A polyphase network according to claim 17, wherein said 1 to h impedance transformer includes in each of said circuits the base of said transistor in said associated one of said circuits being directly connected to the collector of said transistor in an adjacent one of said circuits receiving as an input signal a signal leading in phase with respect to the phase of the input signal coupled to said associated one of said circuits.
 19. A polyphase network according to claim 17, wherein said l to 1/h impedance transformer includes in each of said circuits the base of said transistor in said associated one of said circuits being directly connected to the collector of said transistor in an adjacent one of said circuits receiving as an input signal a signal lagging in phase with respect to the phase of the input signal coupled to said associated one of said circuits. 